When receiving signals, such as biphase modulated (BPSK) or quadraphase modulated (QPSK) suppressed carrier signals, hereinafter generally referred to as PSK (Phase Shift Keyed) signals, it is necessary for the demodulation and recovery of the carrier signal to utilize a circuit such as a Costas demodulator. It is characteristic of this type of demodulator that during acquisition, the carrier tracking loop may false lock at a frequency that is displaced from the true received carrier frequency by an amount equal to plus or minus a harmonic or a subharmonic of the clock frequency of the data channels. Unless positive steps are taken, apart from the conventional structure of the demodulator, the false lock will be maintained and the data cannot be recovered.
A method of removing this likelihood of false lock is to use some form of frequency discriminator to positively drive the voltage controlled oscillator (VCO) of the demodulator to the correct frequency so that phase locking will occur only on the desired received carrier frequency. Apparatus to accomplish this is described in U.S. Pat. No. 3,768,030, entitled "Automatic Signal Acquisition Means For Phase Lock Loop With Anti-Sideband Lock Protection", issued Oct. 23, 1973. A further improvement on this structure is disclosed in U.S. Pat. No. 4,188,589, entitled "Automatic Signal Acquisition Means For a Phase Locked Loop With Anti-Sideband Lock Protection", issued Feb. 12, 1980. In the latter patent two all-pass networks are included with are designed such that a 90.degree. phase shift is produced in a signal passing through one of the networks with respect to a signal passing through the other of the networks. When outputs of these two networks are multiplied the resulting low frequency response is essentially a constant positive voltage when the incoming carrier frequency is greater than the VCO frequency and a constant negative voltage when the received carrier frequency is below the VCO frequency, whenever the frequency difference between the incoming carrier frequency and the VCO frequency lies between a lower frequency, f.sub.L, and an upper frequency, f.sub.H, for the apparatus. This step function discriminator can be designed to override any false lock voltages that could be developed by the phase locking circuits.
Below f.sub.L the discriminator characteristic becomes linear and vanishes within the loop bandwidth of the phase locked loop. Above f.sub.H the discriminator action also vanishes. f.sub.H is chosen to encompass the expected offset frequency plus the modulation bandwidth. f.sub.L is chosen to be below any false lock points and above the phase locked loop (PLL) bandwidth. In the latter case where incompatibility exists a compromise choice of f.sub.L will lead to an acceptable solution.
In this prior art structure two problems arise. First, when the received carrier is modulated at a data rate large compared to the carrier frequency offset the step function nature of the discriminator becomes nominally linear with greatly reduced gain. In these instances false locks may occur. Second, when the modulation is a biphase (Bi.phi.) (or Manchester) format the gain may be reduced to zero. In these instances false locks will occur. Thus, in these prior art devices the frequency discriminator action is dependent on the modulation of the received signal.